Conventionally, as a technique for multi-threading that executes a program while switching a plurality of threads, a multi-threaded processor having a time-out register is suggested. In the multi-threaded processor, when an active thread is executed over an allowable period of time for a program, thread switching is forcibly conducted.
As an example of the related art, Japanese National Publication of International Patent Application No. 2001-521216 and Japanese National Publication of International Patent Application No. 2001-521215 are known.